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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z #

Download Quartus II 11.0.157


You can choose the most efficient mode of operation of the memory
controller, changing its settings. Added a debugging tool for the
transceiver (Transceiver Toolkit). Improved user interface manager
channels enables real-time monitor link status of receivers and
transmitters. Enhanced control panel lets the channels on the fly to
change the parameters of transceivers and see how it affects the
system.
All this allows developers to rapidly build and debug the board.
There was a better means of rapid establishment of the project instead
of QSys SOPS Builder. Allows you to quickly connect QSys-compatible
IP-Cores blocks into a single system.
Additional improvements:
+ Improved Chip Planner (As for the settings of transceivers Stratix
FPGA V);
+ adds support for 64-bit Windows and Linux for the DSP Builder
+ added another IP Core - Deinterlacer II IP core
+ improved support for Cyclone IV GX FPGAs and MAX V CPLDs (see
final timing model can be generated and POF).
+ Finally Improved the problem with the Cyrillic alphabet in a text
editor!))
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