Quartus* II software version 10.0, the industry's #1 software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs, is now available. Download Quartus II software today!. Version 10.0 supports Altera's new high-performance, built-for-bandwidth devices: Stratix* V GX and GS FPGAs with integrated 12.5-Gbps transceivers. Stratix V GX FPGAs are optimized for high-performance, high-bandwidth applications. Stratix V GS FPGAs target high-performance, variable-precision digital signal processing (DSP) applications with the industry-first variable-precision DSP block. Future Quartus* II software releases will also support partial reconfiguration, a Stratix V FPGA feature that reduces power, cost, and board space with more effective logic planning.
Version 10.0 continues to deliver Quartus II software's productivity advantage:
• 2X-3X faster compile times than the nearest competitor for high-density designs
• New transceiver toolkit with real-time transceiver interface and bit-error rate testing capability
• Expanded Rapid Recompile support for more compile-time savings with better timing preservation
• Enhanced QXP file for creating and maintaining an internal custom intellectual property (IP) library for design reuse
• New Self-Service Licensing Center, your one-stop shop for all software and IP license needs
Straix V GX / GS FPGA Support
Quartus II software version 10.0 demonstrates distinct performance and productivity advantages with Stratix V FPGAs. Software enhancements plus the Stratix V FPGA architecture deliver advantages that the nearest competitor cannot:
• 2X-3X faster compile times
• Two full speed-grade advantage, on average
• Greater than 90 percent logic utilization
• 30 percent lower power (vs. previous-generation devices)
Quartus II software offers complete design flow support for Stratix V FPGAs, including:
• Advanced place-and-route algorithms enabling industry-leading compile times and the highest logic utilization
• TimeQuest timing analyzer for easier timing closure
• Incremental compile to finish designs faster and get started in using partial reconfiguration
• PowerPlay power optimization for automatic minimization of power consumption
• SOPC Builder and DSP Builder for faster system design development
• MegaCore* function IP library for reducing design and test time
New Productivity Features
The transceiver toolkit helps you verify transceiver signal integrity before or in parallel with application design development. It can quickly maximize signal timing margins and eye openings by instantly fine-tuning transceiver parameters and viewing the bit-error rate effects.
High-speed designers can access all the transceiver settings--including pre-emphasis, equalization, VOD, and sampling position--using the transceiver toolkit's GUI. You can also check and verify bit-error rate without purchasing a bit-error scope.
Enhanced Rapid Recompile now works with Quartus integrated synthesis for small design changes. The capability delivers an average 50 percent compile time reduction (compared to a full compile), and performs better timing preservation with consistent results. In addition, Quartus II software now supports 8-core processors with multiprocessor support, delivering, on average, a more than 20 percent compile time reduction.
Flexible Design Reuse
Quartus II version 10.0 introduces an enhanced QXP file for greater flexibility in design reuse with support for both post-synthesis and post-fit netlist. This flexible new design-reuse flow facilitates design reuse by creating a custom component library. With new post-fit netlist support, your team can easily increase productivity by shortening development and verification time.
New Self-Service Licensing Center
Use the new online licensing center to set up or manage your software and IP licenses more easily and quickly. View, modify, generate, and manage your licenses 24 hours a day and 7 days a week. The center is available to Quartus II Subscription Edition users. With Quartus II software version 10.0, you have a new licensing mechanism, simplified ordering process, and easy-to-read license file. Visit the Licensing Center today.
• Easier Synopsys design constraint (SDC) entry, with a new “Getting Started Wizard”
• New IP and expanded IP Base Suite -- New 10 Gigabit Ethernet media access control (MAC) and XAUI PHY MegaCore functions are available in version 10.0. The new DDR2/DDR3 controller MegaCore functions, which support ALTMEMPHY and UNIPHY, are both included in the Subscription Edition as part of the IP Base Suite.
• Expanded synthesis support – Quartus II software maintains its leadership in language support by enhancing VHDL-2008 support with a more flexible HDL language structure.
• Enhanced configuration support – Industry-standard, quad serial peripheral interface (SPI) flash devices and enhanced bitstream-compression scheme for faster configuration are also supported.
• Expanded operating system (OS) support – This is the first production release of Quartus II software Web Edition for Linux in version 10.0. Quartus II software now supports Windows 7 and has added SUSE Enterprise 11 support in addition to version 10 support.
• Enhanced Quartus II software GUI – More native look-and-feel on the Linux OS platform.
• Stratix V GX/GS FPGAs – Adds initial advanced support for the new EP5SGXA3, EP5SGXA4, EP5SGXA5, EP5SGXA7, EP5SGXB5, EP5SGXB6, EP5SGSB7, and EP5SGSB8 devices
• Stratix IV GX/ E FPGAs – Adds device programming (POF) support for EP4SGX70 /110 and EP4SE820
• Cyclone IV E/GX FPGAs – Additional pin-out and device programming (POF) support
• Arria II GX FPGAs – Additional support for I3 devices
• HardCopy IV GX ASIC – Full handoff support for HC4GX35 and HC4GX25
• Advanced support – includes compilation and pin-out support
• Programming support – includes compilation, pin-out, and device programming (POF) support
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