Renewing professional program designed for the design of microprocessor devices with a high degree of integration, including the development of complete systems on a single programmable chip.
Altera Corporation - one of the largest developers of ASIC (specialized for a particular task integrated circuit (IC)), programmable logic integrated circuits (FPGAs), was founded in 1983 the company is part of an index of stock price S & P 500 and NASDAQ stock is identified by abbreviation ALTR. As the company without its own production facilities, Altera is focused primarily on the development of circuits and modules based on hardware description languages such as VHDL, Verilog and own AHDL. In the chip production is working with various manufacturers.
Main products - programmable chips, and services to transform the projects under the FPGA to ASIC for mass production. The company also produces programs for developing embedded software for the FPGA, as well as compilers core processor under its own design.
Software Quartus ® II provides support for the best sequence of development of systems based on FPGA, the most advanced technology systems development and integration of IP, placement and routing, timing and methodology of the closed test, which helps to retain the position of leader of Altera Corporation in the CPLD design, using easy to use complete development environment from entering the draft before CPLD synthesis, placement, routing and verification.
Software Quartus II software interface equipped with MAX + PLUS ® Look @ Feel, which allows thousands of developers CPLD to take advantage of Quartus II, without the need to develop new user interface.
Altera Quartus II 9.1 further strengthens the leadership program, supporting devices and Stratix II family and the families MAX ® II, adding and expanding new opportunities for contributing to the improvement and simplification of use and accelerate the design and verification cycles.
Overview and features of the program complex Altera Quartus II 9.1: - Special features:. Support for families of FPGA. The option of the user interface MAX +. File one-time assignments (. Qsf). RTL Viewer. Support changes in the compilation. Formation of a sequence of clocking internal memory. New option technique "balanced" optimization. Function improved synchronization SignalTap ® II
- API: Allows users to use the MAX + provided by Quartus II possible, not bothering to study the new interface. Will Quartus II is installed first, or will be installed later, the user will see the dialog box that allows "see-and-feel (look-and-feel)» choice: Quartus II or MAX +. However, the user may at any time to change this choice.
- Viewer: The new RTL Viewer program files Quartus II provides a schematic representation of the possibility of VHDL and Verilog RTL files, which can be used to analyze the structure of the project prior to the stages of behavioral modeling, synthesis, placement and routing. RTL Viewer allows the developer to manage the hierarchy of the project and place individual items of interest to simplify debugging and optimization. Selected in the viewer RTL elements can be directly traced to the source file
- Changes to compile: Allow developers to experiment with different settings and assignments compile the project. With plants, assignments and compiling the results can be stored and processed separately as a version of the project.
- Formation of a sequence of clocking internal memory: The compiler function memory Quartus II program could be implemented to simplify the use of FPGA embedded memory through the ability to dynamically generate a sequence of pulses required for the operation of the read / write RAM and FIFO, based on selected configurations. Such opportunity is provided MegaWizard ® Plug - In Manager.
- The function improved synchronization SignalTap II
To assess the state of signals in the forthcoming device can be used logic analyzer SignalTap II, allowing to find the cause of defects in the design of the system. Levels of switching reported SignalTap II logic analyzer to capture data on the moment, so if you can not create the conditions change that would capture the relevant data, the logic analyzer will not help you debug the project. Function improved synchronization SignalTap II provides a graphical user interface that allows developer to easily organize a very complex condition synchronization.