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Download ALTERA QUARTUS II v10 SP1 ACDS-EcHoS


Professional software solution, which unite in themselves all the modern tools for the development of innovative microprocessor-based devices on a single programmable chip. Altera Corporation was founded in 1983 and now - is one of the largest companies, developers, ASIC, specialized in software for specific tasks to develop integrated and programmable logic integrated circuits. The main direction of the company - programmable chips, as well as services to transform the projects under the FPGA at ASIC for mass production. In addition, Altera Corporation produces software program for developing embedded software for the FPGA, as well as the compiler for the core processors of its own design. Currently, Altera Corporation Corporations activity is focused primarily on the development of circuits and modules based on hardware description languages such as VHDL, Verilog, and self-AHDL.

Software solution Quartus * II 10.0 provide the best support for the coherent development of systems based on FPGA, the most advanced technology systems development and integration of IP, placement and routing, timing and methodology of the closed test, which helps keep the leading position of Altera Corporation in CPLD design, using easy-to- application, a complete development environment from entering the draft until it CPLD synthesis, placement, routing and verification.

Quartus II software equipped with the software interface MAX PLUS * Look @ Feel, which allows thousands of CPLD designers to take advantage of the complex without the need to develop new user interface.

Altera Quartus II 10.0 further strengthens the leadership program, supporting a series of Stratix II and MAX II, adding and expanding opportunities, contributing to improve and simplify the use and accelerate the design and verification cycles.

The main features of the software solution Altera Quartus II 10.0: - Support for Series FPGA

- User Interface MAX

Software interface helps users to use the provided MAX Quartus II 10.0 possible, not bothering learning a new interface. Will Quartus II is installed first, or will be installed later on, the user will see a dialog box that allows you to look-and-feel choices: Quartus II or MAX.

- Picture of single assignment (. Qsf)

- Tool show RTL files

Provides an opportunity schematic representation of VHDL and Verilog RTL files that can be used to analyze the structure of the project prior to the stages of behavioral modeling, synthesis, placement and routing. RTL files viewer allows the developer to manage the project hierarchy and place individual items of interest to simplify debugging and optimization. Selected in the viewer RTL file elements can be directly traced to the original project file.

- Support for changes to compile

Ability to change the compilation allows developers to experiment with different settings compile at all stages of project development. Group plants, assignments and compile the results can be stored and processed separately as a version of the project.

- Formation of a sequence of internal memory clock

Compiler could be used for ease of use built into the FPGA memory, due to the ability to dynamically generate a sequence of pulses required to read / write RAM and FIFO, based on selected configurations. Such opportunity is provided MegaWizard Plug - In Manager.

- Methodology "balanced" optimization

- Improved synchronization SignalTap II

To assess the state of signals in the developed device can be used by the logic analyzer SignalTap II, which allows to find the cause of defects in the system design. Switch-level logic analyzer report SignalTap II of the moment of data capture, so if you can not create the conditions for change that will capture the relevant data, the logic analyzer will not help you debug the project. Function improved synchronization SignalTap II provides a graphical interface that allows developers easy enough to organize a very complex condition synchronization.

- Starting with version 10.0, from the Altera Quartus II simulator built deleted and the editor of the timing charts. Instead, they recommend using an external simulation language descriptions ModelSim-Altera firm Mentor Graphics (a free version of the ModelSim-Altera Starter Edition).

- Support for Series Startix V GX and Stratix V GS;

- Support for hardware description languages VHDL-2008.;

- Library of IP-cores enriched with several new features, including 10 Gigabit Ethernet MAC.

- Transceiver Toolkit.

Using Transceiver Toolkit, developers can evaluate the signal integrity of high-speed interfaces, and the intensity bit errors in the transmission before the start or in the process of developing their project.

Install

1. Unpack & Burn/Mount

2. Follow instructions in EcHoS dir. EnjoY